"Practically speaking, every SOC design closure takes not only a significant amount of time and effort, but multiple iterations as well. Using ICScape’s physically-aware timing tool TimingExplorer™, and Skipper™, their chip finishing capability, we reduced the number of iterations by at least 50% on each SOC design. And we have reduced clock tree power by almost 40% in one of multimedia chip using optimized clock constraints generated fromClockExplorer."
"Over the last two years, we have successfully used multiple analog and mixed-signal tools such as Aeolus™ ,Aether ™ and iwave™, from ICScape. Aeolus™’s parallel simulation (multi-threading) capability has significantly improved our design productivity without losing accuracy. After tens of successful tape-outs, the tools are being used on every design prior to tape-out. MPS has adopted the tools as its main design platform corporate wide. "
MPS - Dr. Zachary Yao, CAD Director
"Tapeout is one of the major functions that a design support team handles. It requires engineers to review customers’s data, check DRC results and make corrections. Engineers have to compare GDSII data frequently to ensure the logic operations made on the designs are correct. Skipper™ provides a unique platform which enables engineers to finish tapeout work in a single, unified infrastructure platform. It’s specially optimized for massive GDSII data import, export, viewing and its FlashLVL capability enhanced our productivity dramatically."
HLMC - Henry Liu, Director of Design Service
“I am very glad to see the True SPICE simulation tool ALPS has facilitated our IP designs and R&D projects. We expect the cooperation to provide better services for IC design and manufacturing, bringing extensive benefits to our customers.”
Dr. Weiran Kong, Technology R&D and Design Services EVP
